1. Field of the Invention
The present invention generally relates to the design of cache controllers for caches in computer systems in which there are variations in memory access latencies among the memories from which data is cached.
2. Description of the Related Art
Current practice in the design of set associative caches for computer systems is to use a predetermined and fixed replacement method in order to select a line to replace within a set when there is a cache miss that maps to the given set. For example, in a four-way set associative cache using LRU (least recently used) replacement, in order to handle a cache miss that maps to a given set, the cache controller would select the least recently referenced cache line among the four lines in the set to replace. The LRU information is encoded in the cache directory in this case, and the cache controller hardware updates the cache directory LRU information for each cache access. For speed, the replacement method is implemented as hardware logic. Although the design of caches, cache directories, and cache controllers has been extensively studied, an underlying assumption has been that the replacement method is fixed and implemented as hardware logic in the cache controller.